EECS 105 IC Technology
https://www.eecs.berkeley.edu/~boser/courses/105_2004_fa/spice.htm
Parameter
|
NMOS
|
PMOS
|
Unit
|
Cox |
5
|
5
|
fF/μm2
|
μ |
400
|
200
|
cm2/V-s
|
kp = μ Cox |
200
|
100
|
μA/V2
|
VTH |
1
|
-1
|
V
|
γ |
1
|
-1
|
V1/2
|
Φp |
-0.3
|
0.3
|
V
|
λ @ L=1μm |
0.01
|
0.01
|
V-1
|
Col |
0.5
|
0.5
|
fF/μm
|
Cj |
1
|
1
|
fF/μm2
|
Cjsw |
0.1
|
0.1
|
fF/μm
|
Ldiff |
2
|
2
|
μm
|
SPICE:
models and examples
Notes: “Real” IC technologies are described by many more
parameters (50 to 200 per transistor!) obtained from measurements taken from
actual devices (see, e.g.,
BSIM). Of course in practice these would not be “whole” numbers and also
have some variation. For example, the threshold voltage for the n-channel
transistor in a 0.25μm process might be specified as 550mV…675mV. Any transistor
with a threshold voltage in this range would be considered by the foundry as
meeting the specification. One of the challenges for circuit designers is
finding circuits that are insensitive to such variations. We will keep that off
for now, motivation for taking other circuit design classes in the future. For
105, the idealized technology described in the table shown above is a
good start.
|