*
.param wnmin='0.36u'
.param wpmin='2*wnmin'
.subckt INV vin vout vdd vss
M1 vout vin vss vss  nmos l=0.24u w='wnmin'
M2 vout vin vdd vdd  pmos l=0.24u w='wpmin'
.ends

.subckt NAND3 Vdd Gnd VinA VinB VinC Vout
Mp1 Vout VinA Vdd Vdd pmos l=0.24u w='wpmin'
Mp2 Vout VinB Vdd Vdd pmos l=0.24u w='wpmin'
Mp3 Vout VinC Vdd Vdd pmos l=0.24u w='wpmin'
Mn1 Vmid1 VinA Gnd Gnd nmos l=0.24u w='wnmin*3'
Mn2 Vmid2 VinB Vmid1 Gnd nmos l=0.24u w='wnmin*3'
Mn3 Vout VinC Vmid2 Gnd nmos l=0.24u w='wnmin*3'
.ends

.subckt Sram Vdd Gnd vword vbit vbitbar
M0 2 5 Vdd Vdd pmos L=240E-9 W=360E-9 AD=273.599990319867E-15
+AS=273.599990319867E-15 PD=1.7999999499807E-6 PS=1.7999999499807E-6 M=1
M1 Vdd 2 5 Vdd pmos L=240E-9 W=360E-9 AD=273.599990319867E-15
+AS=273.599990319867E-15 PD=1.7999999499807E-6 PS=1.7999999499807E-6 M=1
M2 2 5 0 0 nmos L=240E-9 W=480E-9 AD=165.599996280845E-15
+AS=288.000011209114E-15 PD=779.999993483216E-9 PS=1.67999996847357E-6 M=1
M3 0 2 5 0 nmos L=240E-9 W=480E-9 AD=288.000011209114E-15
+AS=165.599996280845E-15 PD=1.67999996847357E-6 PS=779.999993483216E-9 M=1
M4 vbit vword 2 0 nmos L=240E-9 W=360E-9 AD=273.599990319867E-15
+AS=165.599996280845E-15 PD=1.7999999499807E-6 PS=779.999993483216E-9 M=1
M5 5 vword vbitbar 0 nmos L=240E-9 W=360E-9 AD=165.599996280845E-15
+AS=273.599990319867E-15 PD=779.999993483216E-9 PS=1.7999999499807E-6 M=1
.ends


*.subckt NOR Vdd Gnd VinA VinB Vout
*Mp1 Vout VinA Vdd Vdd pmos l=0.24u w=0.6u
*Mp2 Vout VinB Vdd Vdd pmos l=0.24u w=0.6u
*Mn1 Vout VinA vmid Gnd nmos l=0.24u w=0.72u
*Mn2 vmid VinB Gnd Gnd nmos l=0.24u w=0.72u
*.ends

