*** phase ii
.lib '/home/ff/ee141/MODELS/g25.mod' TT
.inc  'logic.sp'

*****************************************
* Parameter   
*****************************************
Vdd vdd 0 2.5

xinv1 vin1 vin2 vdd 0 INV 
xinv2 vin2 vin3 vdd 0 INV M=3.6923

xnand1_b1 vdd 0 vin3 vin3 vin3 vin4 NAND3 M=2.0449
xnand1_b2 vdd 0 vin3 vin3 vin3 x NAND3 M=2.0449
xnand1_b3 vdd 0 vin3 vin3 vin3 y NAND3 M=2.0449
xnand1_b4 vdd 0 vin3 vin3 vin3 z NAND3 M=2.0449

xinv3 vin4 vin5 vdd 0 INV M=7.5504

xnand2_b1 vdd 0 vin5 vin5 vin5 vin6 NAND3 M=2.028
xnand2_b2 vdd 0 vin5 vin5 vin5 a NAND3 M=2.028
xnand2_b3 vdd 0 vin5 vin5 vin5 b NAND3 M=2.028
xnand2_b4 vdd 0 vin5 vin5 vin5 c NAND3 M=2.028
xnand2_b5 vdd 0 vin5 vin5 vin5 d NAND3 M=2.028   
xnand2_b6 vdd 0 vin5 vin5 vin5 e NAND3 M=2.028    
xnand2_b7 vdd 0 vin5 vin5 vin5 f NAND3 M=2.028    
xnand2_b8 vdd 0 vin5 vin5 vin5 g NAND3 M=2.028 
cwire vin5 0 1.8641f

xinv4 vin6 vout vdd 0 INV M=7.431

xsram0 vdd 0 vout vbit0 vbitbar0 Sram
xsram1 vdd 0 vout vbit1 vbitbar1 Sram
xsram2 vdd 0 vout vbit2 vbitbar2 Sram
xsram3 vdd 0 vout vbit3 vbitbar3 Sram
xsram4 vdd 0 vout vbit4 vbitbar4 Sram
xsram5 vdd 0 vout vbit5 vbitbar5 Sram
xsram6 vdd 0 vout vbit6 vbitbar6 Sram
xsram7 vdd 0 vout vbit7 vbitbar7 Sram
xsram8 vdd 0 vout vbit8 vbitbar8 Sram
xsram9 vdd 0 vout vbit9 vbitbar9 Sram
xsram10 vdd 0 vout vbit10 vbitbar10 Sram
xsram11 vdd 0 vout vbit11 vbitbar11 Sram
xsram12 vdd 0 vout vbit12 vbitbar12 Sram
xsram13 vdd 0 vout vbit13 vbitbar13 Sram
xsram14 vdd 0 vout vbit14 vbitbar14 Sram       
xsram15 vdd 0 vout vbit15 vbitbar15 Sram       
xsram16 vdd 0 vout vbit16 vbitbar16 Sram    
xsram17 vdd 0 vout vbit17 vbitbar17 Sram                                    
xsram18 vdd 0 vout vbit18 vbitbar18 Sram
xsram19 vdd 0 vout vbit19 vbitbar19 Sram
xsram20 vdd 0 vout vbit20 vbitbar20 Sram
xsram21 vdd 0 vout vbit21 vbitbar21 Sram
xsram22 vdd 0 vout vbit22 vbitbar22 Sram
xsram23 vdd 0 vout vbit23 vbitbar23 Sram
xsram24 vdd 0 vout vbit24 vbitbar24 Sram
xsram25 vdd 0 vout vbit25 vbitbar25 Sram
xsram26 vdd 0 vout vbit26 vbitbar26 Sram       
xsram27 vdd 0 vout vbit27 vbitbar27 Sram       
xsram28 vdd 0 vout vbit28 vbitbar28 Sram    
xsram29 vdd 0 vout vbit29 vbitbar29 Sram                                    
xsram30 vdd 0 vout vbit30 vbitbar30 Sram
xsram31 vdd 0 vout vbit31 vbitbar31 Sram
*cout vout 0 12.60438f
C1 vout 0 6.69927960000001E-15 M=1.0 
C3 vout 0 4.60027200000002E-15 M=1.0 
**// analysis
Vin vin1 0 pulse(0v 2.5v 0.1n 50ps 50ps 5ns 10ns)
*Vin vin1 0 pulse(0 2.5 1p 1p 1n)
.tran 0.01ns 16ns
.options post=2 nomod
.op
.meas tran tplh trig V(vin1) val='(2.5*.5)' rise=1 targ V(vout)
+ val='(2.5*.5)' rise=1
.meas tran tphl trig V(vin1) val='(2.5*.5)' fall=1 targ V(vout)
+ val='(2.5*.5)' fall=1

.meas tran trise trig V(vout) val='.1*2.5' rise=1 targ v(vout) 
+ val='.9*2.5' rise=1
.meas tran tfall trig V(vout) val='.9*2.5' fall=1 targ v(vout)
+ val='.1*2.5' fall=1

.meas tran tp param='(tphl+tplh)/2'   
   
.end

